The present invention relates to semiconductor devices and more particularly to high-voltage high-speed semiconductor devices that include at least a silicon-on-insulator (SOI) substrate having at least two or more metal oxide semiconductor field effect transistors (MOSFETs) formed in the active region of the SOI substrate. The present invention is also directed to a process of fabricating a high-voltage high-speed SOI-containing device as well as a circuit which contains the same.
High-speed SOI complementary metal oxide semiconductor (CMOS) and, in particular, partially-depleted SOI (PDSOI) technology requires thin (20 to 300 nm) body thickness in order to provide speed advantages to CMOS circuits. Unfortunately, this very constraint on body thickness also places numerous tradeoffs and compromises in fabrication of coexisting high-voltage devices which frequently are required for higher-voltage interfaces for input/output functions or for non-volatile random access memory (RAM) drivers embedded in high-speed circuitry. For example, tradeoffs and compromises in areas such as breakdown voltage, on-resistance and manufacturing ease and reliability may have to be made and taken into consideration when designing and fabricating a high-voltage high-speed semiconductor device. As is known to those skilled in the art, improving one parameter, such as, for example, breakdown voltage, will result in the degradation of another parameter such as on-resistance. In an ideal high-voltage high-speed semiconductor device, no tradeoffs and compromises would be made.
In today""s generation of high-voltage high-speed semiconductor devices, SOI devices are replacing their bulk Si counterparts since SOI devices provide higher performance, little or no latch-up and higher packing density. In SOI technology, a relatively thin layer of semiconducting material, e.g., Si, overlays a layer of insulating material, e.g., a buried oxide region. This relatively thin semiconductor layer, which is referred to herein as the active region of the SOI substrate, is generally the area in which active devices are fabricated. For example, in high-performance SOI logic devices, the logic devices, i.e., MOSFETs, are built within this relatively thin Si region of the SOI substrate to minimize source/drain capacitance.
Despite the advantages obtained using SOI technology, prior art high-speed SOI devices are not able to withstand high operating voltage, i.e., breakdown voltages of 3V or above. Instead, the maximum operating voltage in prior art high-speed SOI devices has been limited to less than 2.5V. This is because the body of the MOSFET in such prior art high-voltage semiconductor devices is floating, or at best connected to a ground potential via a very high-resistance which in turn gives to relatively low drain-to-source breakdown voltage, Vbds.
Moreover, when high-operating voltages are employed in prior art high-voltage high-speed SOI semiconductor devices, the drain of the MOSFET leaks current into the source, via the body, which causes the device to breakdown.
In view of the drawbacks with prior art high-voltage high-speed SOI semiconductor devices, there is a continued need for developing new and improved SOI semiconductor devices in which higher operating voltages than heretofore possible with prior art SOI semiconductor devices can be employed. That is, an SOI semiconductor device is needed which exhibits a Vbds, that is above 2.5V, preferably above 3V.
One aspect of the present invention relates to a high-voltage high-speed SOI semiconductor device which comprises:
an SOI substrate including at least an active region disposed on an electrically insulating region;
a plurality of diffusion regions in said active region, separated by, and abutting a plurality of body regions in said active region, a first one of the body regions and its abutting diffusion regions having a first width and successive ones of the body regions and their abutting diffusion regions having successively smaller widths; and
a plurality of gates each over one of the plurality of body regions and separated from the body regions by a dielectric material, said plurality of gates connected to a common voltage terminal.
In the present invention, the diffusions between gate regions extend vertically through the entire active region of the SOI substrate.
In one embodiment of the present invention, the diffusion region at the first terminal end of the SOI semiconductor device is a drain terminal and the diffusion region at the other terminal end of the device is a source terminal.
Another aspect of the present invention relates to a circuit which comprises:
a first field effect transistor, said first field effect transistor including a first source, a first drain, a first gate and having a first channel width; and
a second field effect transistor, said second field effect transistor including a second drain coupled to the first source, a second source, a second gate electrically coupled to said first gate, and a second channel width smaller than the first channel width.
In one embodiment of the present invention, the circuit includes a third field effect transistor comprising a third drain region coupled to the second source region, a third source region, a third gate electrically coupled to the first and second gates, and a third channel width smaller than the second channel width. Additional field effect transistors may also be employed in the present invention and the circuit would follow the above design pattern.
A yet further aspect of the present invention relates to a method of forming the above-mentioned high-voltage high-speed SOI semiconductor device. Specifically, the method of the present invention comprises the steps of:
(a) providing a structure including an SOI substrate having at least two patterned gate stack regions on a surface thereof, said SOI substrate having an active region on a buried oxide region;
(b) forming an oxide layer on all exposed surfaces of said structure;
(c) selectively masking a portion of said structure, whereby a first terminal portion of said structure is left exposed;
(d) forming a first diffusion region in said active region of said SOI substrate by ion implanting through said first terminally exposed portion of said structure;
(e) forming a plurality of diffusion regions of the same conductivity type as that of said first diffusion region in said active region of said SOI substrate by ion implanting through portions of said structure not covered by said gate stack;
(f) selectively masking a portion of said structure, whereby the active regions between the gate stacks are exposed; and
(g) forming a deep diffusion region in said active regions by ion implanting through said exposed portion of said substrate.
Optional shallow extension, halo, and/or deep implant steps may be employed in the present invention prior to conducting step (d) above. In accordance with the present invention, each of these diffusion regions would have a width smaller than the first diffusion region.